The invention relates to integrated circuit voltage regulators, and in particular to a linear voltage regulator having a fast load transient response.
Series pass voltage regulators are commonly used for providing a regulated low-noise output voltage from a higher input voltage to a load. Conventional voltage regulators generally include a combined integrator and proportional gain stage for controlling the output voltage. The integrator portion of the combined stage eliminates DC errors and the proportional gain portion of the combined stage permits adjustment of the overall loop gain to ensure loop stability. Often, the output load of the voltage regulator changes dynamically during normal operation of the circuit, sometimes varying from 100% to 0%, or 0% to 100% of the output current level in a matter of microseconds. Conventional voltage regulators typically respond relatively slowly to these load transients.
Designers also attempt to reduce noise levels at the output of the voltage regulator. Increasing load capacitance reduces noise levels at the output. However, the control loop of the conventional voltage regulator may become unstable if a large value of capacitance is coupled to the output. As a result of this relationship, designers must trade off noise and stability.
A voltage regulator method and circuit according to the invention provides a regulated output voltage to a load. The voltage regulator includes a series pass device that provides the regulated output voltage in response to a control signal. A sense circuit generates a sense voltage based on the regulated output voltage. An integrator stage receives a first reference voltage and the sense voltage and generates an integrated signal. A proportional gain and summer stage receives the sense voltage, the integrated signal, and a second reference voltage and generates the control signal to control the regulated output voltage.
In other features of the invention, the integrator stage and the proportional gain and summer stage have a combined gain approximately between 20 and 40. The integrator stage has a total gain approximately between 2 and 5. The proportional gain and summer stage has a total gain approximately between 5 and 10.
In still other features of the invention, the series pass device is selected from the group of PMOS transistors, PNP transistors, NMOS transistors, and NPN transistors. The integrator stage is selected from the group of active integrators and charge pump integrators. The sense circuit is selected from the group of buffers, direct connections, amplifiers, and passive networks.
In yet other features of the invention, the integrator stage includes an integrating circuit in series with a first inverting amplifier. The proportional gain and summer stage includes an amplifier in series with a second inverting amplifier. The series pass device includes an inverting transistor, the proportional gain stage includes a summing circuit in series with a second inverting amplifier, and the integrator stage includes an integrating circuit in series with a first inverting amplifier.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.